This invention relates to a semiconductor memory device capable of reading data in synchronization with a clock signal.
SDRAM (synchronous DRAM) is a clock-synchronized, fast-access MOS semiconductor memory device. Fujiwara and others show a column address decode circuit for SDRAM with high speed and low power capabilities ("A 200 MHz 16 Mbit Synchronous DRAM with Block Access Mode," 1994 Symp. on VLSI Cir. Dig. of Tech. Papers, pp. 79-80). In accordance with this technique, column-select line activation is made by an AND signal of a column decode signal (i.e., an AND signal of plural predecode signals) and an internal clock signal. The column-select line is activated in synchronization with a clock leading edge and deactivated in synchronization with a clock trailing edge subsequent to that clock leading edge.
The above-described column decode circuit however has some drawbacks. For example, if 256 column-select lines are arranged, then 256 AND circuits must be driven by internal clock signals. This increases the clock driver load. The power dissipation increases and the speed of operations including clock drive operations decreases.